资源列表
verilogfifo
- verilog HDL实现先进先出栈，不含测试文件-verilog HDL achieve first-in first-out stack, non-test document
verilog 的串行通讯
- 已编译通过，很使用哦
baskterballconter
- 这是一个关于篮球24秒计数的Verilog程序，程序中包含了开始，暂停，复位键。-This is a matter of 24 seconds count basketball Verilog procedures, the procedures included in the start, pause, reset button.
UART
- UART是一种通用串行数据总线，用于异步通信。该总线双向通信，可以实现全双工传输和接收。在嵌入式设计中，UART用来与PC进行通信，包括与监控调试器和其它器件，如EEPROM通信。-UART is a universal serial data bus for asynchronous communication. The two-way communication bus, can achieve full-duplex transmit and receive. In embedded d
preambledeassemble
- its useful for dissembler data from continuous stream of transmitter data stream
counter
- Counter module that implements the counter module in VHDL.
hightfrquencydivider
- 用VerilogHDL语言实现一个被除数为8位，除数为4为的高效除法器，实现高效的除法功能-VerilogHDL language with a dividend of 8 bits, the divisor is 4 for the high divider, a high efficiency of the division function
fir_lms
- verilog语言编写LMS（最小均方误差）自适应滤波器。-verilog language LMS (least mean square error) adaptive filter.
clock
- 一个简单的数字时钟Verilog仿真程序，60秒1分钟，60分一小时，24小时一天，265天一年。代码逻辑简化不含状态机，易理解。附激励文件可直接仿真。-A simple digital clock Verilog simulation program 60 seconds, 1 minute, 60 hours, 24 hours a day, 265 days a year. The code logic simplifies excluding state machine, easy to
div_clk
- 一个20M转16M的时钟分频设计的小程序。有一定的漏洞请大家自行修正-A 20M to 16M clock frequency applet. There are some loopholes Please correct itself
vhdlforlab
- vhdl语言程序的a244器件的程序 希望对大家的学习有所帮助-VHDL language procedures a244 device procedures for all of us want to be helpful to learn
fenpinqi
- 经典的分频器程序设计，分辨对偶数倍分频和奇数倍分频进行了EDA的程序编写，通过这两个程序，可写出所有的分频器设计-Classic divider programming, identify multiple points on the dual-frequency and odd multiples of the sub-frequency EDA programming carried out by these two programs can be designed to write all