资源列表
16bitADC
- verilog实现的16位模数转换器参考源代码-verilog to achieve 16-bit ADC reference source code
sinclvboqi
- 该程序实现了sinc滤波器的分数延迟速率变换器，其中R = 0.75.-The program implements a sinc filter fractional delay rate converter, where R = 0.75.
VHDL
- 已经开发成产品的步进电机定位控制系统的VHDL程序-Has developed into a product positioning stepper motor control system VHDL procedures
spmem.tar
- Sinlge port RAM VHDL/Verilog design
bram_test
- Hex file to Binary file conversion using VHDL
spi
- SPI 时序逻辑 功能简单 希望大家看看吧-SPI timing logic is simple hope that we see it
spi_ip
- SPI总线的IP核，可以实现半双工spi通信-SPI bus IP core, can achieve half-duplex communication spi
tlc_work_9
- Traffic light controller a four way logic implemented using cpld
vhdl_record_array.tar
- vhdl code for record array package
xor_encryption
- A simple XOR encryption using verilog.
ADCcontrol
- 利用c控制adc，主要是控制字写入，状态控制。
VerilogCode_BCD_counter
- Verilog Code for a BCD counter and it is implemented on Altera DE2 board-Verilog Code for a BCD counter and it is implemented on Altera DE2 board