资源列表
final
- this vhdl code is for a 4th floor elevator control.
interleaver_Matlab_Verilog
- Matlb和verilog编的两个文件。是关于OFDM通信中的交织。-Matlb and verilog OFDM communication interleave
chuankou
- 串口，电脑可接受，可发送；fpga实验主板通过串口线同样可接收发送-Serial port, the computer is acceptable, can be sent fpga board experiments also can be received via the serial line to send
test_i2c_1
- Testbench for an i2c controlling an I2c slave device
kevin_timer
- FPGA 上的数字秒表及完整的显示功能。
accumulator.rar
- 实现累加器的verilog源码，广泛应用在通信电路设计中,The realization of accumulator Verilog source, widely used in communication circuit design
vga_control
- this a spartan 3E base project file. this is the project of game in which vga is interfaced to FPGA. this file is main file in which vga timing is maintained.-this is a spartan 3E base project file. this is the project of game in which vga is i
crc32_8
- crc32,数据位宽为8，verilog编码-crc32，datawidth is8,coding by verilog
usbfifo
- 一种USBfifo的传输方式。控制数据向USB端点中传输数据，-A transfor way for USB，control the data to endpoint.
THS1206
- FPGA来实现数据采集，AD采用TI公司的THS1206，高速并行AD，内含16字FIFO，降低硬件复杂度。-FPGA to realize data acquisition, AD using TI company s THS1206, high-speed parallel AD, containing the 16-character FIFO, to reduce hardware complexity.
rax2
- rax2 fft implation the fft in verilog instance and in ise of xilinx it show how to istance fft core and the port used
test_mac_loopback
- 用来测试MAC地址回环的VERILOG程序，可以继续完善它-Loop used to test the MAC address of the VERILOG program, you can continue to improve it