资源列表
clock
- 用verilog实现数字时钟，测试过基本上满足要求，适合初学者学习-Use verilog digital clock
Arinc_708_Rxer
- arinc_708 source code is here aupdated with brief explanation
SPI_Master
- verilog HDL 语言描述的8位并行转SPI程序-verilog HDL language descr iption of the 8-bit parallel transfer SPI program
8to3
- 8對3編碼器 解多工器 用於整合 可輕易改成16對4-8 3 encoder demultiplexer for integration can be easily changed to 16 pairs of 4
1
- 基于FPGA的USB接口设计，实现了USB与FPGA的通信-USB interface to FPGA-based design, implementation of the USB communication with the FPGA
3ASF_SameData10110-11001_Console
- Sparten-3A收发_间隔产生相同分组10110-11001_控制程序，用于发送数据包。-Sparten-3A transceiver _ interval produce the same grouping 10110- 11001_ control program, used to send packets.
mean
- 3x3 Average filter in VHDL
xhlb
- 数字信号的滤波电路VHDL描述,用于对输入的信号进行数字滤波-Digital signal filter circuit described in VHDL
LCD
- FPGA用于LCD12864的显示程序，采用并行接口，显示固定内容-verilog for 12864 screen
shuizhongvhdl
- 这时一个数字钟的VHDL程序，有计时、校时、整点报时功能，很适合做EDA设计之用-When a digital clock in VHDL procedures, time, school hours, the whole point timekeeping function, it is suitable for use in EDA Design
conversions
- 我在尝试上传一系列对初学者有用的code。 该code可以帮助学习者学习如何用VHDL进行信号类型的转换-I m trying to upload a series of useful code for beginners. The code can help learners to learn how to use VHDL achieving signals type conversion
ccccc
- 串口通讯的例子 串口通讯的例子-examples of serial communications example s of serial communications serial communications examples examples of serial communications