资源列表
wb_tdm_tb
- test bench that qualifies an avalon slave to wishbone interface right through to the end component
Calender
- 万年历，可以准确统计并显示当前的年月日等日期时间-Calendar, you can have accurate statistics and displays the current date and time date etc.
lcd1
- 液晶显示器控制程序，用于初学者练习altera 开发板的液晶显示控制功能-LCD display control program for beginners to practice altera development board LCD control functions
colorchecker
- coloecheck VGA格式标准色卡生成，可支持任意分辨率设置 verilog-colorchecker VGA format standard color card production, can support any resolution settings
hc595
- HC595并串转换程序，Verilog语言编写，经过硬件平台测试-HC595 and string conversion process, Verilog language, after testing the hardware platform
jop_core_cache
- JOP的内核缓存源码，不易找到，大家一定要顶啊-JOP kernel source code cache, not easy to find, we must kits
ram_test
- 实现cpld *存储器,并实时测试内存的好坏.可嵌入到系统中
time
- 用单片机及位LED数码管显示时分秒，以及24时的计时方式运行。能够整点提醒（短蜂鸣，次数代表整点时间），使用按键开关可实现时，分调整，秒表/时钟功能转换，省电（关闭显示）及定时设定提醒（蜂鸣器）等功能-With the microcontroller and LED digital tube display minutes and seconds, and 24 hours of run time. Reminded that the whole (short beep, the number
UART
- FPGA Verilog UART 通信源代码-FPGA Verilog THIS IS A UART SQC
code
- 用dff方法实现二分频，行为描述实现二分频，二分频，投票代码，有限状态机-Dff method used to achieve two-way, behavioral descr iptions to achieve two-way, two-way, voting codes, finite state machine
div
- 利用Ｖerilog实现定点数的除法，在此基础上可考虑实现定点数的除法-Using Verilog to achieve set division points, on this basis can be considered fixed points of the division to achieve
Adder
- 一个加法器的FpGA设计代码 fpga adder-fpga adder