资源列表
FIFO24_CS8416[1]
- Fifo buffer vhdl code
lose
- 基于FPGA的VGA显示历程，自己修改过参数-FPGA-based VGA display course, modified parameters
files
- floating point testbench
shiyan3lcd
- 基于verilog,在LCD上显示汉字，-Based on verilog, the LCD display Chinese characters,
SPIIF
- SPI control interface for LCD driver
serial-to-parallel
- 学习串并转换的代码编写，认识编写风格和技巧，fpga官方网站的代码设计，可直接使用，通过了仿真-Learning string and converts the code written to recognize the writing style and skills, fpga official website of the code design, can be used directly, through simulation
divider.rar
- A divider implemented in VHDL
divider
- 用VERILOG实现一个被除数为8位、除数为4位的高效除法器-With VERILOG implement a dividend for the 8-bit, 4-bit effective divisor divider
decoder_ca
- coder for different modules in verilog
i2c
- i2c配置adv7180 将模拟信号转成数字信号bt656-i2c configuration adv7180
ln
- vhdl写的自然对数计算，通过cordic迭代出的结果。提高精度需要增加迭代次数。-write vhdl natural logarithm, cordic iterate through the results. Improve the accuracy of the need to increase the number of iterations.
radix-4-divider
- Radix 4 Divider in VHDL