资源列表
adc_control
- 控制ADC08D1000，用于2G采样数据-Control ADC08D1000, sampling data used for 2G
da_fir
- 8阶对称系数FIR滤波器分布式算法的实现代码-8-order FIR filter symmetric coefficient distributed algorithm implementation code
3
- simple code based on verilog shifter , cla ,clg
QPSK
- qpsk调制解调的VHDL源代码，已调试成功，可放心使用。-qpsk modulation and demodulation of the VHDL source code ，which has been debugged and can be freely used.
divider_testbench_vhdl_611508553
- 分频器的testbench测试，可联合仿真使用-Divider testbench test
main
- this file is used for sdk implementation in echo server application-this file is used for sdk implementation in echo server application
traffic
- 基于FPGA的交通灯控制系统，使用verilog语言书写，quartus II运行-FPGA—veriliog,Light controlor system
52_divider
- 多倍（次）分频器 请注意: 本例的各个源描述的编译顺序应该是: 52_divider.vhd 52_divider_stim.vhd-Times (times) divider Please note: This case is described in various sources to compile the order should be: 52_divider.vhd 52_divider_stim.vhd
apb2ahb
- verilog code for apb to ahb convert
vgaz2
- 用VHDL实现VGA信号控制的源代码 状态机 -VHDL implementation of the VGA signal with source code control state machine
jishuqi
- 实现计数和分频，用于高精度频率计数器的设计，在一个模块内实现-frenquent cnt
FIR_beh
- FIR滤波器的行为级VHDL源代码，可以任意修改滤波器级数，滤波器系数的精度为16比特。-FIR filter behavioral VHDL source code, which could be amended filter series. The filter coefficients for the 16-bit accuracy.