资源列表
VHD
- 低电平脉冲状态的捕抓（多个）缓存并 用减小的并口线输出
ADS8328
- 高速精密ADC，TI公司的ADS8328的FPGA控制程序，使用verilog语言-High-speed precision ADC, TI s ADS8328 control program the FPGA using verilog language
vhdl_case
- 这是一个两个状态机的文件 都是很输入有关的 是我很我的同学的 希望对大家还是有点帮助的 -This is a two state machine documents are related to the importation of my classmates I hope all of you a little help
clk_dly
- 用于信息传输时的时钟延时程序，可根据使用情况修改部分内容。-choose a person for a job； make use of personnel； need hands
CS5361_DAT
- CS5361 ADC 驱动程序,其中还有时钟部分,这里是数据采集部分. 使用VerilogHDL编写,在Libero中编译,使用Actel芯片测试通过.-CS5361 ADC drivers, of which there are clock parts, here is the data collection using VerilogHDL written, compiled in Libero using Actel chip test.
CSA
- carry save adder vhdl
ElectronicCodeLock
- 设计一个通用电子密码锁，具体功能如下：[1]数码输入 [2]数码清除 [3]密码更改 [4]激活电锁 [5]解除电锁-The design of a universal electronic code lock, the specific features are as follows: [1] digital input [2] Digital Clear [3] Password Change [4] to activate electric lock [5] the lifting
song
- 使用Qutus下载后可在硬件上实现乐曲《友谊地久天长》-Use Qutus download music in the hardware realization of " Auld Lang Syne"
digital6counter_top
- 文件描述的是VHDL语言实现的16位计数器，可用于实现时钟的分频或中断控制-Document describes the VHDL language to achieve 16-bit counter can be used to achieve clock frequency or interrupt control
UART
- 51单片机之间的双机通讯程序，对学习单片机的UART具有很好的参考价值-51 two-machine communication between the microcontroller program for learning microcontroller UART has a good reference value
fifo-verilog
- 用verilog 编写的fifo（先入先出队列）代码 内含测试文件 test bench-First Input First Output programme which designed by verilog codes,including test bench
run_flash
- 实现闪灯功能，在开发板运行时，通过按键来实现闪灯的目的。-Achieve flash function, run on a development board, through the key to achieve the purpose of the flash.