资源列表
LED_0000_9999
- 7段数码管动态显示0000-9999,vhdl语言-7-segment LED dynamic display of 0000-9999, the VHDL language
song
- 用EDA技术实现音乐的自动播放，此源代码用的是VHDL语言，-EDA technology with automatic music player, the source code using the VHDL language,
Codeur_SP
- quadrature encoder state machine
pwm_1M
- 1MHz,16级PWM信号发生器——基于verilogHDL-1MHz,16level PWM signal generation based on verilogHDL
mainctrl
- 自己编得地铁售票系统，而且可能有点小bug，输入纸币，输出硬币，基本功能都有了。
flowadd
- 两个浮点数相加的加法器，使用verilog编写
interleaver-vhdl.rar
- VHDL编写的基于FPGA的4-8交织器代码，有需要的下来看看,4-8 prepared VHDL code interleaver
sva_assetion
- 学习SVA的最基本的例子，对于想了解systemverilog assertion的相关人员非常有用！-SVA learn the most basic example, the systemverilog assertion would like to know the person very useful!
cs5550
- 基于FPGA高精度数据采集系统，采用cs5550高精度AD芯片，本程序主要实现对cs5550的控制。-FPGA-based high-precision data acquisition system, using high-precision cs5550 chip AD, the procedures for the main control on the cs5550.
juxing
- 利用FPGA编写程序控制液晶显示器显示矩形！-Prepared using FPGA control rectangular LCD display!
miffile
- 用matlab产生mif文件。(Altera的EDA软件，如maxplus，quartus等用到的初始化rom，ram等的文件格式)-Mif files generated by matlab. (Altera' s EDA software, such as maxplus, quartus used to initialize and so on rom, ram, such as the file format)
Behavioral-Modeling
- A Code that illustrates 12 bit switch, 2x1 Mux, 2x4 Decoder in behavioral modeling in Verilog HDL using modelsim IDE