资源列表
filter_VHDL
- FIR filter design using VHDL for 32 bit signed coefficientand 32 bit input and decimation is 4 and its working good
07_dled
- 实现数字字母的显示。。等等。。可以输定设置时间等等，还可以做时钟计时输入-Alphanumeric display.. And so on. You can set a time loser, etc., can also do clock input
fir filter vhdl code
- FIR filter design using Matlab Coefficient file and RTL design for FIR filter Design
Uart design with application file
- user defined Baudrate with changing in run time
counter
- 实现技术功能，由待测信号触发使能，在时钟clk的控制下统计计数。-Technological functions, is triggered by the measured signal is enabled, under the control of the clock clk statistics count.
ecpu
- It is a type of RISC processor..it is easily reconfigurable and virtualizable.it is implemented on FPGA
risc16f84_latest.tar
- iT IS A 16 bit RISC processor,,It is easily virtualizable and reconfigurable.It is implemented in FPGA.
ckey_led
- 拨码开关驱动控制LED 如果拨码开关推上去1,那么点亮LED1 如果拨码开关推上去2,那么点亮LED2-DIP switch drive control LED If the DIP switch is pushed up one, then lit LED1 If the DIP switch is pushed up to 2, then lit LED2
dled
- 通过程序编写实现动态数码管显示实验，挨个显示1，2，3，4，5，6，7，8-Dynamic digital tube display through programming experiments, one by one show 1,2,3,4,5,6,7,8
key_led
- 读取按键信号实验 如果按下的是key1,那么点亮LED1 如果按下的是key2,那么点亮LED1-LED2 以此类推，如果下按key8，那么全部点亮8个led-Reads the key signal experiment If you press the key1, then lit LED1 If you press the key2, then lit LED1-LED2 So, if the next press key8, then all eight led
Clk50M_div_1HZ
- 分频实验，将50M时钟分频为1HZ，输出LED1，闪亮-Crossover experiments, 50M clock divider is 1HZ, output LED1, shiny
bram_shift_reg_w16x3072
- 使用 xilinx blockram 做连续shift 在图像处理中 做多行缓存很方便-Using blockram Xilinx as a continuous shift in the image processing to do more than the cache is convenient