资源列表
ModelSim_TestBench_VHDL
- ModelSim TestBench的VHDL模版-ModelSim VHDL template TestBench
dds
- 直接频率合成器，采用verilog hdl-Direct frequency synthesizer using verilog hdl
sanjiaoxing
- 用FPGA编写程序，控制液晶显示器产生三角形！-With FPGA programming, control liquid crystal displays have a triangle!
fifo-interface
- fifo(1-6:1):using ip-code and rd wd interface-fifo:using ip-code and rd wd interface
led_water
- FPGA 流水灯Verilog HDL.-FPGA flow light Verilog HDL.
Prat4
- This code allows an application timing and generation of waveforms: sine and triangular
AD
- ad7667的高速采集程序，采样率800kbps,16位精度采样-ad7667 high-speed acquisition procedures, sampling rate of 800kbps, 16 bit accuracy sampling
multiplier
- this source code is one example to build multipler in verilog HDL.
zerojustv
- 我自己写的过零点判断模块，经过调试效果很理想-I wrote it myself to determine zero-crossing module, after testing the effect of very satisfactory
farrow
- farrow滤波器verilog代码，完成分数倍的抽取-farrow filter verilog code to complete the fractional extraction
CPU_16.rar
- vhdl语言的16b cpu代码 全部的代码我会依次上传 另有说明txt文本,VHDL language 16b cpu code all the code I will upload the text otherwise stated txt
list_ch03_12_hex2led
- This VHDL convert a hex number to seven segments codes.