资源列表
ENCODE_8B_10B
- 8B-10B编码，Verilog代码，通过编译，仿真，代码规范，清晰-8B-10B code, Verilog code, through the compilation, simulation, code specifications, clear
PoE_2temac_TOP
- 基于xilinx公司生产的FPGA可编程逻辑芯片的千兆网卡的设计代码。-1000Mhz Ethernet TEMAC xilinx fpga vhdl RTL
traffic
- 模拟交通灯变化过程控制的VHDL程序，用红黄绿LED灯表示交通灯，用数码管显示状态剩余时间-Control procedures and VHDL simulation traffic lights change process, with red, yellow, and green LED lights, traffic lights, with a digital display of the status of the remaining time
signal-energy-time--test
- 信号到达时间、脉宽检测，能量检测代码，包含tesebench测试文件-The signal arrival time, pulse width detection, energy detection code, including the tesebench test file
SRAM
- sram读写验证，用verilog写成，简单-sram module for test
VHDL_DMF
- Vhdl实现扩频通信匹配滤波器，书上打下来的,打了好久.-VHDL realization of spread spectrum communication matched filter, books, playing down, playing for a long time.
sbox
- verilog code for s-box generation for AES algorith
divisor_n_bits_sin_restauracion
- vhdl divisor of n-bits without restaurecion metod. divisor de nbits en vhdl sin restauracion. con testbench.
FPGA-imitate-RS232
- FPGA仿RS232通讯接口，因FPGA一般无串口，故可设置用户I/O模仿串口功能-RS232 communication interface FPGA imitation, because usually no serial FPGA, it can set user I/O port features mimic
CONTROLLER.vhd
- Controller source code for double data rate sdram1
ulpi_port
- ULPI UTMI conversion
16-bit数的偶数奇偶校验
- 16-bit数的偶数奇偶校验及阶乘运算，用verilog写-16-bit number of even parity and factorial computation, written using Verilog