资源列表
seq_detector
- 3比特的任意二值序列检测器(例如101、110、001等)。从任意序列中检测出三比特的序列。包含VHDL源码以及testbench测试源码程序。-The 3-bit binary sequence of any detector (e.g., 101,110,001, etc.). A three-bit sequence is detected from an arbitrary sequence. Includes VHDL source code and testbench test so
verilog
- 用verilog写的代码，已经过调试，可以试用一下。-Verilog code used to write, has been testing, you can try.
0000000000000
- 这是一个简单的滤波程序，可以完成高频信号的滤除～-This is a filter programme!
decoder
- 对于通信传输中常用的曼彻斯特编码给出了详细的Verilog程序，程序在Modelsim中调试通过。-For the transmission of commonly used Manchester coding are also given Verilog process, the process of debugging in Modelsim through.
HappyBirthday.v
- 基于Virtex-5的Happy Birthday程序 Verilog-Virtex-5-based the Happy Birthday procedures Verilog
24c01
- 基于Verilog-HDL的硬件电路的实现 9.4 脉冲频率的测量与显示
i2c
- i2c数据传输总线接口的verilog源程序-i2c bus interface procedures verilog
adder
- It is VHDL code of 16 bit adder program, counter and IIR filter
Lmk1000_cfg
- 时钟芯片lmk01010 fpga 配置代码-Clock chip lmk01010 fpga configuration code
Mealy
- VerilogHDL语言实现的Mealy序列检测器-VerilogHDL language of Mealy sequence detector
vga_control
- vga 控制器的verilog 源码 ，fpga上可实现图片的显示-vga controller Verilog source code, fpga achievable picture display
formatter
- Actel 基本VHDl模块源代码，包括BCD、LCD、PLL等-Actel basic VHDL source code modules, including BCD, LCD, PLL, etc.