资源列表
DE2_Default
- DE2在板测试代码，用于测试DE2板子的正常性能(DE2 on-board testing code)
新建文件夹
- verilog语言编写的硬件定时器，测试功能可用(Verilog yu yan bian xie de ying jian ding shi qi, qin ce gong neng ke yong)
ckey_led7s
- 使用verilog语言并用按键操作来控制数码管的显示(Use buttons to control the display of digital tubes)
E_2011
- 生成了一个M序列，适用于2011年全国电子设计竞赛的F题(A M sequence is generated that applies to the F question of the 2011 National Electronic Design Competition)
27_adda_test
- ADDA模块的代码，适用于黑金FPGA开发板，35M采样速率(The ADDA module code applies to the black gold FPGA development board, the 35M sampling rate)
12864
- lcd12864静态显示，不可实时显示数据。(The lcd12864 static display, cannot display the data in real time.)
KEYPD
- Keypad sample. Vhdl language
JBD
- 基本的D触发器，可实现基本的保持功能。输入到输出不变。(The basic D flip flops enable basic retention functions. Input to output remain unchanged.)
T_0D
- 带同步清0、同步置1的D触发器模块。希望能够帮到大家。(D trigger module with synchronous clear 0 and synchronous setting 1. I hope I can help you.)
Y_0D
- 带同步置1、异步清0的D触发器。详细的讲解，易懂。(D flip-flop with synchronous 1 and asynchronous clear 0. Detailed explanation, easy to understand.)
m_manche
- 有关于M序列的曼彻斯特编码，亲自验证有效。(The Manchester code of the M sequence is personally validated.)
diver
- 根据芯片的始终频率进行分频，可调节占空比。容易实现。(The frequency division is carried out according to the chip frequency at all times, and the duty cycle is adjusted. Easy to implement.)