资源列表
CPLD-CRACK-SIEMENS-200PLC
- 可用来破解分析西门子200 PLC与模块的通讯协议，基于ALTERA CPLD EPM240的设计. 需要配合分析板配套使用。-Analysis can be used to crack the Siemens 200 PLC and the communication protocol modules, based on the ALTERA CPLD EPM240 design. The need to tie in with the analysis supporting the
ethtoe1
- 硕士论文 基于FPGA的Ethernet+over+E1接口芯片的设计与实现.pdf-master paper the design and implentation of Ethernet+over+E1
modelsim57e
- Verilog编写仿真软件，能很好的仿真其他环境的已编译文件-modelsim
PID
- PID控制，采用VHDL代码实现，整个实体模块由三个vhdl文件组成，仅供参考和学习；-PID control, the use of VHDL code, the entire entity vhdl module consists of three files, for reference and learning
Modelsim
- Modelsim 5.6詳細使用教學手冊-Of Modelsim 5.6 using the instruction manual
99-down-count
- 99倒数计数器，利用EDA的专用软体quartus II来编写，程序功能为99倒数计数器，可以自动清0.-99 down counter
verilog_74_2
- 74HC161，74HC194，74HC283，74hc4017，Verilog实现，带实验说明文档。-74HC161, 74HC194, 74HC283, 74hc4017, Verilog implementation, with test documentation.
vgatutorial13
- 这个主要是用VHDL语言来实现从xilinxFPGA中的RBOM中读取一幅图像，并通过VGA口显示出来，同时还有加密的功能，按不同的按键可以实现图像颜色转换。-The VHDL language is mainly used in the RBOM from a xilinxFPGA to read an image, and displayed through the VGA port, as well as the function of encryption, the keys can b
shc
- 自己想的写的。。是毕业时候用到。的、、谢谢大家-They want to write. . When used graduation. , And, thank you to see
16128-LED
- 用16*128点阵屏实现时间和温度的显示，此程序非常实用！请尊重版权，不要用于商业目的！-16* 128 dot matrix screen with the realization of time and temperature display, this program very useful! Please respect copyright, do not use for commercial purposes!
watch
- 基于verilog-HDL的电子秒表电路，采用quartusII72编译仿真，经下载测试通过。-Verilog-HDL-based electronic stopwatch circuit simulation using quartusII72 compiled by downloading the test.
part2
- Altera DE2 开发板试验3 第2部分VHDL答案-Altera DE2 Lab3 Part2 VHDL Answer