资源列表
MAC网卡_verilog程序
- 77433649MAC_verilog.rar
basketball
- 30秒篮球倒计时设计程序源码及仿真原码，下载即可用-30 basketball countdown procedures and simulation of the original source code
I2C-Master-_-Slave-Core
- 用verilog 实现的 iic 总线编程，包括master，和slave的编程，很详细的iic总线编程-Iic-bus implemented using verilog programming, including the master, and slave programming, a very detailed iic-bus programming
paomadeng
- 飞思卡尔MC9S12XS128的例程，此文件是跑马灯程序-Freescale MC9S12XS128 routine, the program file is the Marquee
HD6409FPGA
- 一个基于HD6409的编解码的FPGA 开发程序-HD6409 FPGA
1
- 多功能波形发生器 方波（占空比可调） 三角波 -Multi-function waveform generator square wave (variable duty cycle) triangular wave
xapp283
- YUV到RGB的色彩空间转换器(VHDL,Verilog and doc)-Color Space Converter: Y’CrCb to R’G’B’
PPT_Tutorial_ETH
- 瑞士苏黎世大学VHDL课件.对入门初学者有一定帮助。-University of Zurich, Switzerland, VHDL courseware. Of entry to some extent help the beginners.
cmi_code
- 基于VHDL的CMI编码程序，使用VHDL语言编程将NRZ码转换为CMI码-The CMI coding process based on VHDL, VHDL programming language used to convert the CMI code NRZ code
lcd
- 利用FPGA驱动LCD显示中文字符的VHDL程序-Use of FPGA-driven LCD display Chinese characters of the VHDL program
CPU
- 16位简单cpu用VHDL语言实现。里面有好几个的》-16-bit cpu with a simple VHDL language. There are several of the "
miller
- 整个系统分为两个模块：检测模块和解码模块。检测模块主要完成从输入串行序列判断出A，B或C信号，并分别输出脉冲标志脉冲串Signal_A，Signal_B和Signal_C；同时，当检测到任一信号时，BIT_EN_temp输出一个高脉冲。解码模块根据检测模块输出的三个标志脉冲进行0/1解码，输出最终的密勒解码数据DOUT；同时，输出DATA_EN和BIT_EN两个标志信号。-The whole system is divided into two modules: detection module