资源列表
基于VERILOG的uart应用
- 介绍了在FPGA板上的串口调试实验，用verilog语言写的，在NEXYS3板上调试成功
test_pll
- 使用modelsim se6.5d仿真altpll锁相环 完整工程，verilog代码，因为没找到选的是vhdl-simulation pll with modelsim se6.5d
xilinx_cable
- xilinx下载电缆原理图，用于自制下载电缆-xilinx download cable schematic
5SGSD5H3F35C4
- ALTERAL的Stratix5GS系列芯片的电路图、管脚分配、性能手册，方便配置芯片和使用资源-The schematic of ALTERAL the series of Stratix5GS chip, pin allocation, performance manuals, convenient configuration chip and use of resources
DE0_D5M
- 这是在DE0板上实现的用D5M+VGA的图像实时显示程序，完整工程-This is achieved in DE0 board D5M+ VGA images with real-time display program, complete project
tranreceive
- 基于fpga的串口通信，好东西，希望大家喜欢-Fpga-based serial communication, a good thing, hope you like
ADV7180
- files describe how to configure an ADV7180
VerilogHDL
- 用Verilog HDL语言编写的跑马灯小程序，可直接在FPGA上运行-With the Verilog HDL language of the Marquee applet can be run directly on the FPGA
twice_clk
- 对输入时钟进行2倍频 已在modelsim中通过仿真 建议进行后仿 应用上来看 是可以使用的-the function of the module is frequency multiplication，and the module had been test and verified by modelsim,so the products can be employed with 100 ease by each consumer.think you!!!!
一位半加器
- 这是一个用vhdl语言设计的一位半加器以及一位全加器的代码，经过QUARTUS验证可以运行！
clock
- verilog 实现的跑表程序。可以对这个程序加以修改，可是显现电子钟的设计。设计可以根据需要实现分秒。同时可以改成是LED的跑等程序。功能强大的很！-verilog implementation stopwatch program. This procedure can be modified, but the show clock designs. Design can be according to the need to achieve every second. At the same
Uart_Send
- UART的完整发送程序，包括完整的工程核源代码。-UART to send the complete procedure, including the complete source code of nuclear engineering.