资源列表
FPGA_FIFO
- 使用Verilog编写的同步FIFO，可通过设置程序中的DEPTH设置FIFO的深度，FIFO_WRITE_CLOCK上升沿向FIFO中写入数据， FIFO_READ_CLOCK上升沿读取数据。本程序对FIFO上层操作简单实用。-Prepared by the use of Verilog synchronous FIFO, through the setup program in the FIFO depth DEPTH settings, FIFO_WRITE_CLOCK rising
jiangsaidaima
- 这是竞赛代码和历程光盘，是学习嵌入式过程中比较简单的几个实例，在xinlinx环境下实现。-This is a contest code and course CD-ROM, the embedded process of learning a few simple examples to achieve in xinlinx environment.
cpu
- 5 stage pipeline CPU, verilog HDL code-5 stage pipeline CPU
QuartusIIVHDLDDS
- 基于FPGA的DDS信号源设计全部内容，可以输出显示频率-FPGA-based design of the DDS signal source of all content, you can display the output frequency
DEMO_V
- 黑金FPGA开发板（学生）测试程序 VHDL语言 包括led 按键 串口 lcd的检测-Black Gold FPGA development board (student) test procedures VHDL language, including the detection of serial lcd led key
keyscontrol
- 4*3键盘扫描输入，带移位，8段LED灯扫描显示-4×3keys control
Music-Player-by-buzzer
- 基于蜂鸣器的音乐播放器。用于NIOS2里面，基于SOPC Builder开发-Music player based on the buzzer. For NIOS2 which, based on the SOPC Builder development
pump-program
- s7-300泵轮换程序,需要用西门子step7打开-s7-300pump program，It must be open by step7 software
DDR2_ctrl
- DDR2 SDRAM控制器的设计及FPGA验证
eda
- 利用ATMEL公司的QUETUSii软件编写的verilog语言程序，实现一个带复位、调整时间功能的电子钟，以数码管显示时间，调整时间时调整位闪烁-ATMEL Corporation QUETUSii using software written in verilog language program, the realization of a zone reset, adjust the time function of the electronic clock to digital disp
verilogclk
- Verilog HDL语言编写的多功能数字钟.-Verilog HDL language multi-function digital clock.
EPM240
- EPM240的一些相关资料 有原理图 引脚图-Some information has EPM240 schematic pin diagram, etc.