资源列表
dds2_ok
- 利用LPM_ROM和HDL设计的一个DDS信号发生器，分辨率优于1HZ，ROM表长度8位，8位频率控制字。-HDL design using LPM_ROM and a DDS signal generator, the resolution is better than 1HZ, ROM table length 8 bits, 8-bit frequency control word.
ALU_ise10migration
- It s vhdl source code for 32 bit ALU.
LUdecompose
- 基于verilog的LU分解,本文件包括详细的程序代码，运行文件，以及详细的文档-LU decompose based on verilog
pcirw
- quartusII环境下实现FPGA与PCI9054通信。根据PCI9054规范控制lhold、lholda、ads、blast、lbe、lwr等握手信号的时序，可完成上位机通过PCI总线读写FPGA本地地址空间的功能- Communication between FPGA and PCI9054 in QuartusII IDE.Implementation for the timing of handshake signals such as lhold, lholda, ads,bla
IP
- ALTERAL的stratix4的IP核的使用讲解PPT，便于理解Stratix的IP核调用-The IP core stratix4 ALTERAL the use to explain the PPT, to facilitate the understanding the Stratix of IP core call
FDWT
- it explains the ID DWT concepts. and the codes are in VHDL and MATLAB
ad
- STC12C5A60S2的AD转换，并送入LCD显示-STC12C5A60S2 the AD converter, and into the LCD display
VHDLprogram
- VHDL的程序包，包括LED控制，LCD控制、DAC0832接口电路、URAT、FSK\PSK\MASK调制、波形发生器等。适合工程参考-VHDL package, including the LED control, LCD control, DAC0832 Interface Circuit, URAT, FSK \ PSK \ MASK modulation, such as waveform generator. Reference for the project
FSK-VHDL
- FSK调制与解调VHDL程序及仿真，仿真通过-FSK modulation and demodulation process, and VHDL simulation, simulation by
fsk
- FSK的编码 运用VHDL实现代码仿真-FSK encoding
verilog
- verilog实现的数字频率计8位数码管输出显示同时矩形波分档输出-verilog implementation of digital frequency meter
UART
- LM3S系列微处理器异步总线通信例程，有5个-LM3S series asynchronous microprocessor bus communication routines, there are five