资源列表
Verilog_seg7
- Quartus的原理图和.v文件混合输入编程-The mixed input method of schematic File and Verilog HDL File for Quartus II
clock
- 基于VHDL的数字时钟设计，能很好的模拟数字时钟显示-VHDL-based digital clock design, can be a good analog and digital clock display
CycloneIII_EP3C40F780C8_10_One_Wire
- SOPC,CycloneIII系列芯片EP3C40F780C8，NIOS II IDE,单总线实验代码 -SOPC,CycloneIII，EP3C40F780C8，One_Wire code
CycloneIII_EP3C40F780C8_4_Button_LED
- SOPC,CycloneIII系列芯片EP3C40F780C8，NIOS II IDE,按键开灯实验代码 -SOPC,CycloneIII，EP3C40F780C8，button—_led code
decoder_bcd7seg
- Basic 7-segment decoder for Verilog
pwm
- 一个宽度脉冲调制pwm的模板，因为是学习使用的，增加了数据输入以便在开发板的led灯中观看实验现象，输入数据越大led的亮度越大-A pulse width modulation pwm template, because it is learning to use, increasing the data input for viewing experimental phenomena in the development board led lamp, the greater the gre
dds
- FPGA产生dds正弦信号,基于quartus-FPGA generate dds sine signal, based on quartus
pingjie1
- 基于fpga的pi/4dqpsk 调制，用Verilog语言编写(Pi/4dqpsk modulation based on FPGA, written in Verilog language)
ckey_led7s
- 使用verilog语言并用按键操作来控制数码管的显示(Use buttons to control the display of digital tubes)
Data-Sheets
- samsung DDR datasheet
SystemVerilog_3.1a
- SystemVerilog_3a 语言详细手册-SystemVerilog_3a detailed manual language
16_clk_generator
- 简单的任意分频源码,可以通过调节参量改变输出频率-Simply divide any source, the output frequency can be changed by adjusting the parameters