资源列表
fangbo
- 将运动控制卡的方向信号与脉冲信号转换为两路正交方波信号信号（模拟光栅信号）-The direction of the signal and the pulse signal is converted motion control card for two orthogonal square wave signal signal (analog signal raster)
fp
- Verilog分频仿真结合蜂鸣器程序例程，以及仿真测试脚本程序Tastbench.-Verilog simulation combined with buzzer divide routine, and simulation test scr ipt Tastbench.
RS-design-on-FPGA
- RS算法设计在fpga上的实现文章，很详细-RS design on fpga pdf
CD1_PHOTO_ABLUM_1280
- 基于FPGA的数码像册实验，使用了NIOS做文件系统和JPEG图像解码FPGA和SDRAM做了图像缓存-Based on the FPGA digital image book experiment, using the NIOS to do file system and JPEG image decoding FPGA and SDRAM do the image cache
muti_final
- 多时钟周期cpu简单实现,计算机组成实验8-multi circle cpu implement，org of computer lab8
CIC_Filter_Module
- 数字接收机cic抽取模块 抽取倍数可以选择 包括verilog代码 word文档 matlab仿真 testbench代码(CIC decimation module of digital receiver Extraction multiple can be selected Including Verilog code Word document Matlab simulation Testbench code)
cyclone_handbook
- Altera 公司生产的FPGA系列中的低端高性能产品cyclone一代用户手册,这个也能从Altera官方网站上下载。-Altera' s FPGA series production of low-end high-performance products cyclone generation, user manuals, this is also downloaded from the Altera website.
dds
- verilog语言编写，在Quartus II里仿真DDS的产生，包括所有仿真生成的相关文件，-verilog language in the Quartus II DDS in the generation of simulation, including all documents generated by the simulation,
DE2_Synthesizer
- FPGA VHDL PROGRAM DE2_Synthesizer
urat接收程序
- uart串口接收程序，实现基于Rs232传输线的数据的接收。(UART serial receiving program to realize data receiving based on Rs232 transmission line.)
adder_carry_chain
- 使用verilog语言实现进位链加法器,quartus下编译，并使用modelsim进行了验证，内含carry_chain.v代码文件以及testbench文件-use verilog language,carry_chain adder
DDS
- DDS正弦波发生模块 基于verilog语言实现 在cycloneii系列FPGA上经过验证 频率步进1khz 共有256个点-The DDS sine wave module based on verilog language achieve in cycloneii series FPGA proven frequency stepping 1khz 256 points