资源列表
UVM_learning
- UVM使用指南和代码分析，有PDF学习指南文档，还有hello入门级代码供参考-UVM guides and code analysis, study guide in PDF documents, as well as entry-level code for reference hello
Altera_FPGA_develop(QuartusII_7.2_ModelSim_6.5).ra
- Altera FPGA开发说明（QuartusII 7.2 & ModelSim 6.5）.pdf 建立和编译QII项目 modelsim功能仿真 QII引脚分配 modelsim时序仿真（建立Altera仿真库） QII下载 -Altera FPGA Development Descr iption (QuartusII 7.2 & ModelSim 6.5). Pdf project to establish and build QII QII pin ass
eetop.cn_UVM
- UVM 的 入门实例，一个完整的能够跑通的实例。其中包括DUT代码，Testbench代码，(UVM entry example, a complete example of running through. These include the DUT code, the Testbench code,)
ones_counter
- Ones counter for Verilog, basic project for Altera FPGA
verilog-xuexi
- verilog HDL相关的学习资料，对于FPGA与Verilog HDL的初学者有很大帮助。-verilog HDL learning materials for FPGA Verilog HDL beginners.
ndiv
- verilog code for pcounter
yima3_8
- 3_8译码器就是将输入的三位编码转换为8位输出，使其中一位与其他不同，从而实现译码功能(The 3_8 decoder converts the input three bit code to 8 bit output, so that one of the bits is different from others, thus realizing the decoding function.)
PWM
- 基于FPGA的PWM的一小段代码！用VERILOG 写的，主要是控制一盏led灯的亮度问题-Based on FPGA PWM of small pieces of code! VERILOG with written, main is to control a lamp that led lamp brightness problem
fira
- 这是一个用FPGA中DSP Bulider做的一个FIR滤波器，很好使用，我已经测试过了-This is an FPGA, DSP Bulider used to do a FIR filter, a very good use, I have tested the
SDRAM
- SDRAM控制器，Verilog代码编写，让你快速了解SDRAM的读写时序。包含Modelsim仿真工程和学习笔记-SDRAM controller, Verilog coding, allows you to quickly understand the SDRAM read and write timing. Modelsim simulation engineering and contains study notes
SystemVerilog_3.1a
- system Verilog language reference manual
CycloneIII_EP3C40F780C8_7_KB_7seg
- SOPC,CycloneIII系列芯片EP3C40F780C8，NIOS II IDE,七段数码管实验代码-SOPC,CycloneIII，EP3C40F780C8，KB_7seg code