资源列表
AD9512_ISE
- AD9512提供多路输出时钟分配功能，输入信号最高可达1.6 GHz。它具有低抖动和低相位噪声特性，能够极大地提升数据转换器的时钟性能。(AD9512 provide multiplexed output clock distribution function, the input signal of up to 1.6 GHz.It has a low jitter and low phase noise characteristics, can greatly promote the clo
lab2
- Verilog lab2 is used for learning vivado
lab4
- Verilog lab4 is used for learning vivado
lab5
- Verilog lab5 is used for learning vivado
04_led_test
- verilog 入门 流水灯verilog 入门 verilog 入门 verilog 入门(verilog led test xilinx)
05_key_test
- fpga key test 入门 xilinx 黑金的板子(fpga key test xilinx)
07_uart_test
- fpga 串口 Verilog 黑金的板子，入门(fpga uart test xilinx)
11_ddr3_test
- fpga ddr3 sdram verilog 黑金的板子(fpga ddr3 sdram verilog)
13_usb_test
- fpga usb2.0 cy7c68013 黑金的板子(fpga usb2.0 cy7c68013)
syn_dp_fifo.v
- 同步双端口FIFO, 可同时读写，FIFO深度宽度可通过参数配置，带SV断言测试。(Dual Port Synchronization FIFO for ASIC/FPGA)
fpga
- verilg语言实现测频 及与stm32以fsmc通信方式进行通信(Verilg to achieve frequency measurement and communication with STM32 in FSMC communication mode)
CY7C68013固件程序 FPGA测试Verilog程序
- CY7C68013固件程序 FPGA测试Verilog程序(CY7C68013 firmware, FPGA test, Verilog)