资源列表
DDR_FLASH_VHDL_Verilog
- FPGA DDR 外部RAM 读写的verilog代码，以及FLASH的vhdl代码-DDR SRAM READ AND WRITE VERILOG CODE ,FLASH VHDL CODE ,FPGA
1213
- 是十六位乘加器的VHDL语言描述。是我的课程设计。很好用。成绩是优秀-Is a sixteen by adder VHDL language descr iption. My course design. Good use. Performance is excellent
multiplier-accumulator(vhdl)
- 用VHDL语言描述和实现乘法累加器设计,4位的被乘数X和4位的乘数Y输入后，暂存在寄存器4位的寄存器A和B中，寄存器A和B的输出首先相乘，得到8位乘积，该乘积再与8位寄存器C的输出相加，相加结果保存在寄存器C中。寄存器C的输出也是系统输出Z。(原创，里面有乘法部分和累加部分可以单独提出来，很好用) -With the VHDL language to describe the design and realization of multiplier-accumulator, four of
4位乘法累加器
- 4位乘法累加器，有需要的下吧，其他位的可以自行修改~-Multiplication accumulator 4
SRAM_Write_read
- SRAM读写的VHDL实验,通过对写入的数据与读出的数据进行比较,判断读写SRAM是否成功-SRAM read and write VHDL experiments on written data and read data to compare, to judge the success of SRAM read and write
R61526-initial-code
- initial code to set up the R61526 LCD controler
mux4_to_1
- 四选一选择器的Verilog HDL编程，在Quartus II中实现了四选一数据选择器的功能。-Four elected a selector Verilog HDL programming, in the Quartus II in the four election data selector function
DE2_NET
- 基于altera公司EP2C35672C6的DE2板子的光盘中的自带文件。DE2_NET，网络模块。-Based on the DE2 board altera company EP2C35672C6 CD in its own file. DE2_NET, network modules.
tlc5628VHDL
- VHDL实现对TLC5628 AD芯片的时序控制,vhdl对时序的控制不仅高速,而且控制时序清晰,容易实现-vhdl counter tlc5628
cpu
- 给定指令系统的处理器设计,指令字长16位，包含10种操作-Given instruction processor design, 16-bit instruction word length, contains 10 kinds of operations
vhdltestbench
- testbench,VHDL的，适合初学者使用-testbench
rs232
- 基于QuartusII的RS232的串口编程实验，包括有波特率的改变-Based on the RS232 serial port programming QuartusII experiments, including the baud rate change