资源列表
计算机设计与实践实验 16位cpu设计
- 计算机设计与实践实验 16位cpu设计 使用用VHDL语言 -16-bit cpu design with VHDL
Clk50M_div_1HZ
- FPGA的分频功能，从50M到1Hz,FPGA的分频功能，从50M到1Hz-FPGA- divide function from 50M to 1Hz , the FPGA divide function from 50M to 1Hz
VGA(FPGA)
- 基于FPGA的VGA工程文件以及相应的参考资料-FPGA-based VGA engineering documents and the corresponding reference
aescore
- 基于FPGA的AES算法实现的VERILOG源代码，对于信息安全专业研究AES算法的硬件实现很有用-FPGA-based AES algorithm implementation VERILOG source code, for the information security professional research of the hardware implementation of AES algorithm is useful
vhdl
- 包括一个8位D触发器、一个jk触发器、一个10的计数器。适合初学者和开发人员-Including an 8-bit D flip-flop, a jk flip-flop, a 10-counter. Suitable for beginners and developers
S1_38yima
- 利用fpga作为控制器让蜂鸣器实现播放音乐-verilog fpga
coef_reload91
- Altera 的系数可重载的滤波器代码，来自其官方网站-Altera filter coefficients can be overloaded code, from its official website
fenpinq
- VHDL分频器的设计，可以产生奇数和偶数次分频-VHDL Divider
DS1302
- 基于VerilogHDL编写的时钟管理芯片DS1302实验开发程序。-VerilogHDL prepared based on clock management chips DS1302 experimental development program.
LCD12864xianshihanzi
- 12864显示汉字，很好的，在CPLD实验板上通过验证-12864 display Chinese characters, very good, validated in the CPLD experiment board
ping_pong_buffer
- 用寄存器来实现乒乓缓存(Verilog HDL)-Ping-pong with the register to achieve cache (Verilog HDL)
85375524AGC
- Matlab agc 实现 用verilog 编写的的 供参考 AGC 电路增益-Matlab agc prepared to achieve the supply with verilog reference AGC circuit gain