资源列表
16FFT
- 基于FPGA的16点FFT实现VEILOG-FPGA 16FFT VERILOG
VHDL_Testbench
- Altera官方的VHDL_Testbench教程,想学怎么写Testbench的话,强烈建议看一看。（英文的文档，不过都不难。耐心看完吧！）-Altera official VHDL_Testbench tutorial, want to learn how to write Testbench, then strongly recommended that a look. (English document, but are not difficult. The patience to re
SPI_Wishbone_Controller
- FPGA SPI总线硬件描述语言Verilog下的实现-FPGA SPI bus under the Verilog hardware descr iption language to achieve
ec11-test
- 台湾产数字编码电位器EC11的使用测试程序-Taiwan-digital encoder potentiometer EC11 of testing procedures
ads7883
- FPGA实现对ADS7883的控制以及数据采集串行转并行-FPGA implementation of the ADS7883' s control and serial to parallel data acquisition
test_ad9852
- 使用FPGA来控制DDS信号的产生，从而达到高频信号产生的目的。使用的DDS芯片为AD9852，在QuartusII下编写。-Using the FPGA to control the DDS signal generation, so as to achieve high-frequency signal generation purposes. Use of DDS chip AD9852, in the QuartusII prepared.
floatadd
- 浮点数加法器的源代码,实现浮点数的加法功能，浮点数遵循的是IEEE745标准-floating_piont addition
opencore
- 基于FPGA的视觉采集系统的实现，verilog源码-FPGA-based visual collection system, verilog source
statemachine
- 用VHDL实现的有限状态机，还有modelsim仿真文件，及仿真结果-VHDL implementation using finite state machine, there modelsim simulation file, and the simulation results
rs_encorder
- RS编码的fpga实现，详细的vhdl文档，可以硬件实现。-RS coding fpga implementation, detailed documentation of vhdl can be implemented by hardware.
PWM_deadtime
- 利用HDL语言编写的PWM死区时间的实现，已经通过本人仿真验证，对于电力电子行业的研发人员有帮助-Using HDL languages implementation of PWM dead time has passed my simulation, for the power electronics industry, R & D staff to help
22
- 高速QAM解调器的算法及VLSI实现研究，非常不错的一篇论文，对通信行业人员具有一定的参考意义-High-speed QAM demodulator algorithm and VLSI Implementation, very good paper on the communications industry personnel with some reference value