资源列表
SystemVerilog
- 有三篇systemVerilog的经典书，对学习很有帮助(There are three classic books of SystemVerilog, helpful for learning)
uart_test
- 描述了利用spatran6系列的FPGA，进行串行异步通信的uart串口实现代码(Describes the use of spatran6 series of FPGA, serial asynchronous communication uart serial port to achieve the code)
pll_test
- 描述了利用spartan6系列FPGA，实现PLL锁相环的功能代码(Describes the use of spartan6 series FPGA, PLL PLL to achieve the functional code)
Greedy_snake
- 利用SPARTAN6系列的FPGA，实现开发一款基本贪吃蛇游戏，可在显示屏上游戏，采用verilog代码(Using SPARTAN6 series of FPGA, to achieve the development of a basic snake game can be on the screen game, using verilog code)
状态机
- 简单的状态机，按下按钮可在4个状态间进行切换(simple state machine)
加减法器
- 可实现两个4bit补码的加法及减法，有溢出提示(adder with overflow hint)
ex5
- FPGA测试频率，传统测频率,verilog语言，短程序，测频法测频率(using FPGA verilog language a short code for frequtents)
SDRAM
- 使用VHDL语言编写的对SDRAM进行读写操作控制器及其简单的测试层序。(VHDL language used to read and write operations controller SDRAM and its simple test sequence.)
clock_sel
- 无毛刺多时钟选择，可根据不同模式选择不同时钟(Multi clock selection, different modes can be selected according to different clock)
Quartus_12.0_x64
- quartus 12 "solution"
Quartus_12.0_x86
- quartus 12 "solution" 2
QuartusII91_
- quartus 9 "solution"