资源列表
m60component20161109
- 用verilog语言实现的模为60的计数器，经编译合格，利用quarter2及以上可以直接使用，并使用了分块模式(Using Verilog language to achieve the modulus of 60 counters, compiled by qualified, using quarter2 and above can be used directly, and the use of sub block mode)
ad
- 这是用vhdl语言实现ad转换的源码，用quartus实现。(ad transform using vhdl)
FPGA-频率计（等精度测频+SPI通信）
- 本程序采用FPGA编程，实现等精度测频的程序，并且有实现SPI通信的程序。(This procedure uses FPGA programming, such as precision frequency measurement procedures, and to achieve SPI communication procedures.)
main
- 嵌入式系统加密的FPGA实现源码，可直接用于工程(Embedded system encryption FPGA implementation source code, can be used directly for the project)
mcu_led2
- 基于vivado平台，使用microblaze搭建一个小系统，并能点亮led(Based on the vivado platform, the use of MicroBlaze to build a small system, and can light LED)
khatd
- It comprises aircraft flight attitude control, such as slip angle, tilt angle, roll angle, pitch angle, Including AHP, factor analysis, regression analysis, cluster analysis, Face Recognition light treatment method.
fir
- fir 滤波器的程序文件和测试文件，仿真数据和matlab仿真数据进行过比对，matlab采用fdatool生成的低通滤波器，采样率为24兆，通带2.5M，截止频率为5M(FIR filter program files and test files, simulation data and MATLAB simulation data have been compared, Matlab using FDATool generated low-pass filter, sampling rat
ALTERA几个下载方式的介绍
- 介绍ALTERA几种下载方式。主要有JTAG,AS,JIC这几种方式(Introduce ALTERA several download methods.)
iCore3_FPGA_15_UART
- 基于FPGA的UART教程，串口通信实验相关(UART tutorial based on FPGA)
decoder38-ok-38译码器
- 使用quartus2软件的VHDL编写了简单38译码器，希望大家能积极学习(The use of quartus2 software VHDL prepared a simple 38 decoder, I hope we can actively study)
03_SMG
- 实现两位数码管计数功能， 逐渐增加功能，每一秒增加一次，增加到99循环一次。(To achieve two digital tube counting function, gradually increase the function, increase every second, increase to 99 cycles.)
szmb
- 用VHDL语言基于ISE，在XILINX FPGA开发板上编写的数字秒表程序(Using VHDL language, based on ISE, in the XILINX FPGA development board prepared by the digital stopwatch program)