资源列表
verilog
- 蜂鸣器演奏梁柱的verilog代码，本代码已经在EP2C8的开发板上验证过，音质还不错的。-Buzzer playing the beams of the Verilog code, the code has been in the EP2C8 the development board certified, the sound quality is pretty good.
switch
- 运用VHDL语言，实现MAX7317的采集程序，可以将该子模块加载到主程序中。-The use of VHDL language the MAX7317' s acquisition program, this sub-module is loaded into the main program.
chuankou
- 。典型的RS232 信号在正负电平之间摆动，在发送数 据时，发送端驱动器输出正电平在+5～+15V，负电平在-5～-15V 电平。接收器典型的工作电 平在+3～+12V 与-3～-12V 之间。-. Typical RS232 signal level swing between positive and negative, when data is transmitted, the transmitter side driver outputs a positive level in+
uartin
- 串口通信，实现数据的串并转换，以及并串转换-Serial communication, serial and parallel data conversion, and parallel to serial conversion
frequency发生器
- vhdl语言实现的频率发生器，可以产生不同的频率-A frequency generator wirriten by VHDL, which can generate different frequecies.
addersubtractor
- 这是个vhdl编写的16bit的加减法器-This is vhdl prepared by the modified instruments used in the 16bit
cordic_3
- 流水线结构的cordic，可以输出sin/cos
controller
- VHDL code for controller
decode810
- 使用硬體描述語言verilog 的 8b10b-a 8b10b decoder use verilog
CPU_design
- 微机原理32位微处理器设计。可以完成基本的MIPS指令。-Microcomputer Principle 32 of the microprocessor design. You can complete the basic MIPS instruction.
rc5_dec_pre
- encryption with preround(state machine)
STEP
- Routine for a stepper motor with PIC16F8-Routine for a stepper motor with PIC16F877