资源列表
traffic_light
- module traffic(CLK,EN,LAMPA,LAMPB,ACOUNT,BCOUNT)
modelsim
- 利用硬件描述语言Verilog来进行简单的硬件描述，从而设计出一些简单的硬件。-Verilog hardware descr iption language used to describe a simple hardware to design a simple hardware.
UART
- This vhdl code has a simple implementation of an UART receiver. This code was generated march 2011 as a universuty project
Ex07
- 利用ADC0809和DAC0832实现模拟电压信号的采集与输出。-ADC0809 and DAC0832 analog voltage signal acquisition and output.
loopdisp
- 利用CPLD控制六个数码管动态显示所要显示的数值-CPLD to control the use of six LED dynamic display to display the numerical
key
- 用vhdl语言实现des编码中的密钥产生 是des编码中重要的一部分-Des code using vhdl language in the key generation is an important part des coding
ADS7835_2x4
- Module for 2 AD7835 ADC po-Module for 2 AD7835 ADC poll
3ASendReceive_SameData101110_Console
- Sparten-3A收发_间隔产生相同分组101-110_控制程序，用于发送数据包。-Sparten-3A interval produced the same group receive _ 101-110_ control program, used to send packets.
shift-register
- 四位移位寄存器，基于spartan6 fpga开发，移动信息工程学院学习必备，数字设计与计算机体系结构项目-Four shift registers based spartan6 fpga development, mobile learning essential information Engineering, Digital Design and Computer Architecture Project
addsub_core_
- hdl的8051核，不知道好不好用大家试试吧。xilinx公司的核-HDL 8051 nuclear, we know that is really useful to try it. Xilinx's nuclear
p2s16_1
- 前段时间看见有人在网上求并串转换的程序，今天闲了，就编了一个供大家参考一下。 其实是很简单的，只要理清思路，还是很容易的 。
elevator
- C language for 8051 single request elevator