资源列表
pie_encode
- 符合EPC C1G2协议的 数字基带 PIE编码模块源代码-The agreement with EPC C1G2 digital baseband PIE coding module source code
Keyer
- Video Keyer supporting Luminance key, Self key, Matt key and Split key
serialcom
- 串口通信的一个小程序，可以实现与上位机及下位机之间的通信，希望对大家的学习带来帮助-A small program serial communication can be achieved with the host computer and the communication between the lower machine, we hope to bring help to learn
Dip_PB_LED
- 4 bit counter. 1 Push Button (PB) and 1 Dip Switch (DP)are inputs. 4 Leds (common anode) are outputs.
div
- 除法器设计，基于FPGA，实现除法运算，在实物上测试通过-Divider design, based on FPGA, to achieve the division on the physical test
rxd_interface
- 串口接收接口控制，16分频的，和uart——rxd——contrl联合使用-Verilog uart rxdinterface
8QAM
- 8 array QAM design using HDL
lpm_inv0
- 自己编写的vhdl语言来实现的lpm_inv0电路，自我感觉还可以，也通过了编译，如果有需要就下载去看看吧-prepared vhdl own language to achieve the lpm_inv0 circuit, but also a sense of self, also passed the compiler, if there is a need to look at the downloaded Look here
VGA
- 基于Verilog的VGA显示程序 用于实现FPGA对于VGA显示器的控制实现图像显示，并给出相关测试的TB文件-The VGA display program based on Verilog FPGA for implementing the control of the VGA display Image display
qpsk
- qpsk调制解调的FPGA实现。QPSK为调制程序，QPSK-two为解调程序。-qpsk modulation and demodulation of the FPGA. QPSK as the modulation process, QPSK-two for the demodulation process.
FPGA_SPI.ZIP
- 实现了FPGA以SPI协议传送和接受16位数据。传送过程无需Nios核干预-SPI protocol to achieve the FPGA to send and receive a 16-bit data. Nios nuclear transfer process without intervention
VHDL_Somador8Bits
- * FullAdder implementation in VHDL with respectives signals: a, b : in std_logic_vector (7 downto 0) soma : out std_logic_vector (7 downto 0) ci : in std_logic co : out std_logic overflow : out std_logic negativo : out std_logic