资源列表
plc
- 可以实现电子时钟的键盘扫描程序，和LCD程序-Enables electronic clock keyboard scanner, and LCD process
clock
- 用vhdl 实现数字时钟功能，基于fpga实现-Digital clock using vhdl function, based on fpga implementation
eda1
- 根据自己需要输入相应的分频系数，最后仿真得到相应的结果....非常好用-failed to translate
LabA1Design2
- 设计模式比较器电路：电路的输入为两个8位无符号二进制数a、b和一个模式控制信号m；电路的输出为8位无符号二进制数y。当m=0时，y=MAX(a,b) 而当m=1时，则y=MIN(a,b)。要求用多层次结构设计电路，即调用数据选择器和比较器等基本模块来设计电路。-Design pattern comparator circuit: circuit input as two 8-bit unsigned binary numbers a, b and a mode control signal m
cmultip
- 用VERILOG HDL 实现节省乘法器的16位复数乘法器-With VERILOG HDL achieve savings of 16-bit complex multiplier multiplier
Desktop
- 曼彻斯特编码的VHDL语言实现，可以用于RFID防碰撞编码的实现-Manchester encoding of the VHDL language, can be used for implementation of RFID anti-collision code
lpm_mult0
- 在Quartus2的编程环境下以VHDL语言来实现 32*32 的高速计算-Quartus2 programming environment in the VHDL language under 32* 32 high-speed computing
vmm_test
- 怎样在vmm中建立不同的testcase，以测试不同的功能模块-how to build testcase
debounce_logic
- This HDL Module take input from any mechanical switch and give the stable output without glitches.
uart_rx
- quartus.exe 环境下经过编辑和仿真之后，作为FPGA器件的实验用串口接收数据驱动。 -quartus.exe edited and policy environment after the experiment as the FPGA device to receive data-driven serial port.
cordic
- Algorithm for cordic
int_div1
- vhdl编写的任意分频器，经过测试好用，准确-divider vhdl any written, tested easy to use, accurate