资源列表
yimianzhihuan
- 页面置换算法中的三种算法相关程序代码 FIFO LUR OPT-yemianzhihuansuanfa
tube_driver
- 利用altera公司的FPGA使用verilog语言描述了数码管的驱动电路以实现数码管显示功能-Altera FPGA verilog language descr iption of the digital control drive circuit to digital tube display
testbench
- FPGA逻辑实验中，用VHDL语言实现IP核生成的实验。-FPGA logic experiment, with VHDL language implementation IP nuclear generated experiment.
div2
- 32位除法器 被除数和除数均为16位整数，16位小数 商为32位整数，16位小数 余数为16位整数，16位小数 Verilog HDL 代码
6_coder
- VHDL编写！8-3线编码器大全！ 包括 coder8_3.vhd 8线/3线编码器 coder8_3_1.vhd 8线/3线编码器 sn74ls148.vhd 8线/3线优先编码器 coder16_4.vhd 16线/4线优先编码器-VHDL write! 8-3 line encoder Daquan! Including coder8_3.vhd 8 line/3 line encoder coder8_3_1.vhd 8 line/3 line encoder sn7
pinlvji
- 用汇编语言设计的频率计，注释较详细，适于初学者学习使用-Assembly language design frequency meter, the comment in more detail, suitable for beginners to learn to use
TIMER
- FPGA verilog 秒表TIMER功能-FPGA verilog THIS IS A TIMER
VHDL-test-code-divider
- VHDL实验代码：除法器，是一个基于VHDL语言开发的小程序，是关于除法的算法，比较实用-VHDL test code: divider, is a VHDL-based language developed by a small program, on the division algorithm, more practical
PR-QMF
- 实现基于matlab的QMFB的完全重建，是一篇经过仿真且经过测试的正确的代码，可用价值比较高。-Based on matlab QMFB the completely rebuilt, is a through simulation and tested the correct code, can be relatively high value.
Cpu_model
- Verilog HDL编写的CPU模型，很经典，比较通用-Verilog HDL prepared by the CPU model, classic, more generic
VGAimagecontrollor
- VGA图象显示控制器设计,实现在VGA显示器上显示图象.-VGA image display controller designed to achieve the VGA display shows images.
vga_colorblock
- 本代码已成功运行在SPARTAN3E上，通过自行将约束文件与相应的开关映射，即可完成彩色模块的不同显示。-This coding have successed loading on the SPARTAN3E startboard ,you can map the proper UCF file with switch ,so you can see the different color block changing the switch