资源列表
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- verilog HDL文件 PS你们网站做的有点差。。。 verilog HDL文件 verilog HDL文件 verilog HDL文件 verilog HDL文件 -verilog hdlverilog hdlverilog hdlverilog hdlverilog hdlverilog hdlverilog hdlverilog hdlverilog hdlverilog hdlverilog hdlverilog hdlverilog hdlverilog hdlverilog
uart-verilog
- 经典rs232串口Verilog源代码，晶振可随意根据具体情况更改，代码风格非常清晰，明了！-Classic rs232 serial Verilog source code, the crystal can be altered depending on the circumstances, the code style is very clear, clear!
lru_new
- 采用LRU替换算法。这种算法选择最久没有被访问的块作为被替换的块。 为了实现LRU算法，要在块表中为每一块设置一个计数器（cnt0，cnt1，cnt2，cnt3，）。计数器的长度为2位。-using LRU replacement algorithm. This algorithm to choose the most long visit is not being replaced as a block by block. To achieve LRU algorithm, in bloc
GAFF
- 伽罗华域GF（q）乘法器设计,完整的源代码。-Galois field GF (q) multiplier design, the complete source code.
reg-a-wire
- verilog 使用中reg 与 wire 区别及使用方法-verilog using the difference between reg and wire and method of use
serial_in_vhd_data_conversion.
- signal data conversion,signal data conversion
digitPI_control
- 数字式PI比例积分控制器，有关自动控制方面的知识-The digital PI PI controller, the automatic control of knowledge
VGA2
- 实现VGA的显示功能，适合初学者学习参考-Achieve VGA display capabilities, suitable for beginners to learn
multiplyUnit2
- verilog multiply algorithm
vga
- 从fpga到vga输出的verilog程序，信号包括了RGB,VSYNC,HSYNC信号！-the program in verilog from fpga to vga ,which includes the signal of red\green\blue and vsync\hsync.
Desktop.tar
- I ve implemented what oi believe to be a very usefull and easy way to understand the FIFO queue using a DPRAM
seconed-code
- keypad 4x4 with pic18f