资源列表
uart
- 用FPGA实现uart的verilog源码，包含standard framing error, parity control and overrun detection.-The UART design was designed from a standard uart function with a read/write microprocessor interface. It includes standard framing error, parity control and ove
lcd12864
- 用Verilog写得FPGA实现lcd１２８６４的控制程序，在Ｑｕａｒｔｕｓ环境下调试通过-Written using Verilog FPGA implementation lcd12864 control program, the debugging environment by Quartus
usb
- 程序是用VHDL语言在quartus开发环境中实现的usb驱动的源代码-VHDL language program is a development environment in quartus implemented usb driver source code
stopwatch
- 自己写的一个数字秒表，已经在实验板上面验证通过-Write a digital stopwatch, have been verified by experiments above board
17_parity
- 奇偶校验器，对八位二进制数据及其奇偶校验位的输入进行校验，输出正确的奇偶校验位。-Parity, eight binary data and its parity bit input calibration, and output the correct parity bit.
vga_char
- verilog实现vga接口，可以在显示器上显示一个字符，具体显示什么字符可以按自己喜好更改相应数据。-verilog vga interface, a character on the display, and specifically what characters can change the corresponding data according to their own preferences.
sqrtaTB
- Write a HDL Code to find the square-root of the given value.
sch
- 电子系统设计高层次综合high level synthesis 源码,C++ 实现调度-electronic system level HLS design, cpp code for scheduling
clk
- 在DE2上显示时间的程序，包括年月日时分秒，可以设置开始时间，代码在NiosII IDE环境下编写
error_injector_test
- This a vhdl code for error injection code for colour converter fpga program-This is a vhdl code for error injection code for colour converter fpga program
LineBuffer---shifttaps
- 基于移位寄存器的线缓冲，从alt中提取出来，方便使用-Line Buffer。rar
lg
- 基于fpga的逻辑分析仪可显示八路波形，实时分析八路波形 -they simply based on the logic analyzer can show that the Eighth Route Army waveform, real-time waveform analysis of the Eighth Route Army