资源列表
altera_up_avalon_vga
- fpga的vga显示 学生做课程设计或毕业设计的时候可以用到(vga display on fpga Students can use the course design or graduate design)
dovision
- 一个使用的进度条制作实例,你能够方便控制flash的播放等功能！,(Use a progress bar production instance, you can easily control the flash of the play, and other functions!)
FSM
- 有限状态机设计的基本原理、技巧和方法，适合FPGA开发的新人学习(Finite state machine design of the basic principles, techniques and methods for FPGA development of new people learning)
SSH Singapore_7
- yuwyiwehjmmwenvnbwehgusdtwe
i2c_sel
- I2C slave 支持1带多，需要调试是否可用，有问题可以指出。(I2C slave side. Can support more than one band. I have been debugging, sure there is available)
yenyan_v76
- Independent component analysis algorithm reduces the raw data noise, Including quaternion various calculations, Including Deng's correlation, absolute correlation, correlation of slope, improved absolute correlation.
DE2_PS2_Example
- PS2 Module for Altera DE2
Extras_Edge_Detection
- Altera Edge Detection for FPGA
DE2_Basic_Computer
- Convert DE2 FPGA to Small Computer
mmp
- 电子密码锁设计， （1） 设计一个开锁密码至少为4位数字（或更多）的密码锁。(Electronic puzzle lock)
asyn_fifo
- 该源码包是异步fifo的Verilog语言模型，主要包括2个部分：异步fifo控制模块、测试文件。(The source package is asynchronous FIFO Verilog language model, including 2 main parts: asynchronous FIFO control module, test files.)
syn_fifo
- 该源码包是同步fifo的Verilog语言模型，主要包括2个部分：同步fifo控制模块、测试文件。(The source package is a synchronous FIFO Verilog language model, including 2 main parts: synchronous FIFO control module, test files.)