资源列表
blockRomTest
- it is a rom with vhdl
fenpin
- 利用vhdl写的分频程序，芯片是LATTICE的(Using VHDL to write frequency division procedures, the chip is LATTICE)
5828
- Using MATLAB dynamic clustering or iterative self-organizing data analysis, Calculate the multifractal trend fluctuation analysis, LFM pulse compression of the Matlab program.
xc3sprog_rev780_working_with_xc6slx9_spi
- xc3sprog working version see http://xc3sprog.sourceforge.net/ use with https://sourceforge.net/projects/libusb-win32/
VerilogHDL
- Samir Palnitkar-Verilog HDL_ a guide to digital design and synthesis-SunSoft Press (2003)
Palnitkar_Verilog_1996
- Samir Palnitkar-Verilog Digital Design Synthesis-SunSoft Press (1996)
05448528
- s a clean renewable energy, wind energy draws more and more attention around the world. In case of high wind speed or low speed but substantial installed wind power capacity, wind turbine generators (WTGs) will take the place of traditional power
IIC读写EEPROM发送到PC串口
- 能实现用IIC读EEPROM并且将读取的数据通过串口发送到PC端，以及在PC端通过串口发送数据给FPGA，再利用IIC将数据写入EEPROM(The program can realize that FPGA read the data from EEPROM by IIC and then send it to PC by UART,and that PC send the data to FPGA by UART and then write the data to EEPROM by
vga
- fpga控制vga在显示器上的彩条显示()
uartverilog
- FPGA利用串口、FIFO实现串口收发数据(FPGA using serial port, FIFO serial transceiver data)
8_1
- 一个具有置位、复位、左移和右移功能的八位移位寄存器/“01011010”序列检测器。移位寄存器电路端口为：异步清零输入端口rst，输入时钟clk，置数判断输入端口load，移位类型判断输入端口m，数据输入端口data[7:0]，输出端口q[7:0]。序列检测器电路端口为：异步清零输入端口rst，输入时钟clk，串行数据输入端口d，输出标志端口s。(A eight bit shift register / 01011010 sequence detector with set, reset, le
7_1
- 电路端口为：异步清零输入端口rst，输入时钟clk_in，输出时钟clk_out。并分别采用两种以上的方法实现。(Frequency divider circuit port is: Asynchronous Clear input port rst, input clock clk_in, output clock clk_out. And use two or more methods to achieve.)