资源列表
verilog_PLL
- 全数字锁相环的verilog源代码，包括鉴相器，K变摸可逆计数器，加减脉冲器和N分频器。已经仿真实现。(All digital phase-locked loop Verilog source code, including phase discriminator, K variable touch reversible counter, add and subtract pulse and N frequency divider. Have been implemented by simula
Zet-1.3.1
- 在单片FPGA上实现九十年代初期PC，可安装Windows3.1及其他DOS系统。SOC中包含以80286(cpu),中断控制器,显示控制器(VGA),声音控制器,PS2(鼠标，键盘)等。是了解计算机历史变迁及学习SOC设计的重要资料！(ZET aims to implement an early 90`s PC on FPGA.Which include a 80286(cpu),interrupt controller,display card(VGA),sound card,PS2 int
sp6
- 使用赛林思公司fpga开发的8为led流水灯程序。(Using, a company developed by FPGA, is a LED running water lamp program.)
FIFO_ASY
- 异步FIFO，利用格雷码作异步FIFO指针减少亚稳态产生，利用同步寄存器放置亚稳态的级联传播。(Asynchronous FIFO, using gray code for asynchronous FIFO pointer to reduce metastable, cascade propagation using synchronous register placed metastable.)
按键控制led
- 按键控制led灯亮灭顺序，从左到右跑或者从右往左跑(Press button to control the LED lights on and off)
fir
- 电源滤波器是由电容、电感和电阻组成的滤波电路。滤波器可以对电源线中特定频率的频点或该频点以外的频率进行有效滤除，得到一个特定频率的电源信号，或消除一个特定频率后的电源信号。(Power filter is composed of capacitance and inductance and resistance of filter circuit.Specific frequency of the filter to the power cord or the point that the
序列检测器
- 本例子为一个序列检测器的程序，序列为：110010010000100101００，检测的序列为10010(This example is a sequence detector procedure, the sequence is: 11001001000010010100, the detection sequence is 10010)
code.sources
- 秒表代码加上相应的key，测试通过可以直接用于vivado(zcscscsasfsdfsfasfasf)
Verilog HDL（第4版）[王金明][电子教案]
- Verilog HDL（第4版）[王金明][电子教案].rar 注意是ppt教案。(Verilog HDL (Fourth Edition) [] [Wang Jinming].rar e-lesson plans note ppt plans.)
src
- 使用FPGA+DAC产生DDS，可变频率(user FPGA and DAC generate DDS)
pinlvxianshi
- 通过FPGA中的时钟信号分频作为基准频率，将另一频率作为输入与之比较，并在数码管显示输入频率。(The frequency division of the clock signal in the FPGA is used as the reference frequency, the other frequency is used as input, and the input frequency is displayed in the digital tube.)
CNTlum
- 使用Windows7 系统，quartus ii 9.1 软件，Verilog 语言 0到9的计数，并且亮度逐渐增大(count from 0 to 9,and the lum become more and more high)