资源列表
led
- 8位数码扫描显示电路设计（VHDL）通过编译
ADC_16bit
- 16位ADC的verilog源代码 16-bit Analogue-Digital Converter-16-bit ADC verilog source code 16-bit Analogue-Digital Converter
LATTICE_synplifyPro_basic_flow
- LATTICE_synplifyPro_examples_basic_flow.zip,LATTICE 同步工程源码-LATTICE_synplifyPro_examples_basic_flow.zip，LATTICE simultaneous engineering source
IIC
- 硬件语言verilog实现IIC控制器，严格按照IIC协议编写硬件控制器行为及代码-Hardware language verilog realize IIC controllers, written in strict accordance with IIC protocol hardware controller behavior and codeHardware language verilog realize IIC controllers, written in strict acco
asi_framesync
- 从串行TS流中找到同步头,生成标准并行TS流的方法!-Be found in TS stream from the serial sync header to generate the standard method of parallel TS stream!
verilogfile
- 设计一个同步FIFO，该FIFO 深度为16，每个存储单元的宽度为8 位，要求产生FIFO 为 空、满、半满、溢出标志。请采用可综合的代码风格进行编程。-16*8bit fifo
YUV_to_RGB
- YUV to RGB converter in verilog
Latch
- 閂鎖器在FPGA的代表 使用verilog HDL-Latch on behalf of the FPGA using verilog HDL
cpu_4
- 用verlog语言写的4指令CPU的实现，运行于MAX+plusII10.2环境下-Written in four languages with verlog instruction CPU implementation, running on the MAX+ plusII10.2 environment
auto-buy-machine
- 自动售货机的VHDL程序-VHDL program vending machines
de2_audio_if
- audio codec wm8731 wolfsom in verilog. custom project
GFverilog-hdl
- 伽罗华域的乘法器的设计，使用有限域设计乘法器-Galois field multiplier design, the use of finite field multiplier design