资源列表
TheDesignersGuidetoVHDLVolume3
- VHDL, the IEEE standard hardware descr iption language for describing digital electronic systems, has recently been revised. This book has become a standard in the industry for learning the features of VHDL and using it to verify hardware designs. Th
the_designer_s_guide_to_vhdl
- This book is very useful for VHDL designer.
guide
- VHDL的经典书 VHDL的经典书 VHDL的经典书-VHDL classic book classic VHDL book VHDL book VHDL classic book classic classic VHDL book
usb_blaster
- usb下载线usb_blaster，用于cpld\fpga等，刚刚调试完-usb download cable usb_blaster, for cpld \ fpga and so on, had just finished debugging. .
22222222222222222
- 基于FPGA 的数字接收机设计方案，别人的硕士论文，个人认为较好-FPGA-based digital receiver design, someone else' s master' s thesis, think better
ddr2
- 基于Xilinx fpga的ddr2 控制器设计方法-Xilinx fpga-based controller design method of ddr2
Atlys_AXI_Web_Server_Demo_v_1_02
- 赛灵思 Web Server Demo v 1 02-赛灵思 Web_Server_Demo_v_1_02
The Designer's Guide to VHDL, Vol.3, Third Ed
- The Designer's Guide to VHDL, Vol.3, Third Ed.rar
fpga3
- 正在学习FPGA, 这些资料跟大家分享一下.-Are learning FPGA, such information to share with you.
jop
- ALL VHDL FPGA -- THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF -- MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
prj_ex_2
- 锁存器的写法仿真和方法，经过具体的仿真和优化，发现代码完全可用(The method and simulation of the locking device are simulated and optimized, and the code is found to be fully available)
Gameone
- 此秒表有两个按键（reset， start）按下reset键后，秒表清零，按下start键后，开始计时， 再次按下start键后， 停止计时， 用FPGA开发板上的两个七段数码管显示时间（以秒为单位），计时由0 到 59 循环。 高级要求（可选）：实现基本要求的前提下，增加一个按键（select），用于轮流切换两个七段数码管分别显示百分之一秒，秒，分钟。 规格说明： 1.通过按下reset键（异步复位），将秒表清零，准备计时，等检测到start键按下并松开后，开始计时 。如果再次检测