资源列表
UART
- 语言：verilog语言 功能：通过串口控制模块，实现FPGA与串口 通信。 仿真环境：modelsim 综合环境：quartus -Language: verilog language function: through the serial port control module, FPGA and serial communication. Simulation Environment: modelsim integrated environment: quartu
FIR
- FIR结构数字滤波器，64阶。在Altera FPGA上验证通过-FIR digital filter structure, 64 bands. Verified by the Altera FPGA on the
FPGA-basedmultipliersCSDcode
- 基于FPGA的CSD编码乘法器（在MATLAB环境中）-FPGA-based multipliers CSD code (in MATLAB environment)
xapp870
- xilinx v5上sata link 初始化文档-Xilinx Sata link initilization guide
1
- 用VHDL实现地铁售票系统-Use VHDL to achieve subway ticketing system
i8255_verilog
- 8255的Verilog hdl源代码，适合FPGA工程师使用-8255' s Verilog hdl source code for FPGA engineers
lcd12864_avalon_interface
- 12864液晶的ip核，niosII，avalon总线。-12864 LCD ip nuclear, niosII, avalon bus.
count
- 用VHDL实现一个四位十进制计数器来进行计数，并且仿真通过-To use VHDL to achieve a 4 decimal counter to count, and the simulation through the
LVDS
- 高速串行差分接口（HSDI）设计实例,用QUARTUS和利用FPGA实现LVDS的方法。-High-speed serial differential interfaces (HSDI) design example implementation using FPGA LVDS QUARTUS and use of the method.
gh_timer_8254
- VHDL Source code for 8254 timer/counter
gh_vhdl_lib
- VHDL Library for 8254 timer/counter core
de2-sd-mp3player
- de2板上，先存入sd卡，实现的MP3播放器功能-de2，sd2，MP3player