资源列表
Verilog
- 异步fifo的经典写法，使用verilog语言编写的。-Asynchronous fifo' s classic formulation, using verilog language.
SDHAnalysis
- 光纤通信中的SDH数据帧解析及提取的VHDL实现源代码，共包含帧同步、E1及F1码流提取、DCC1码流提取、帧头开销串行输出四个主要模块-SDH fiber-optic communication data frame analysis and retrieval implementation of VHDL source code, include the frame synchronization, E1 and F1 stream extraction, DCC1 stream extra
int_div1
- vhdl编写的任意分频器，经过测试好用，准确-divider vhdl any written, tested easy to use, accurate
clock-a-stopwatch
- 基于DE2-70平台，可实现功能： 1、在LCD上显示时间 2、在数码管上显示跑表-DE2-70-based platform, enabling functions: 1、display time on the LCD 2、display stopwatch the digital tube
SDRAM
- SDRAM控制器，Verilog代码编写，让你快速了解SDRAM的读写时序。包含Modelsim仿真工程和学习笔记-SDRAM controller, Verilog coding, allows you to quickly understand the SDRAM read and write timing. Modelsim simulation engineering and contains study notes
user_logic_0
- 基于microblaze EDK 工程，实现六种RFID 协议的ip core。-Based on microblaze EDK project, to achieve the six RFID protocol ip core.
bei
- 应用VHDL语言写的倍频器，通过对高频信号的分频得到较低频率信号的倍频-Applications written in VHDL multiplier, high-frequency signals through low frequency signal divided by the frequency
TW6816
- TW6816 – 4-CH Audio/Video Decoders with 66MHz PCI interface. Preliminary Data Sheet.
RS-code
- 我测试过的！Verilog HDL实现RS编码。-I' ve tested it! RS coding Verilog HDL implementation.
FPGA
- 5 款fpga开发板原理图和关于fpga的一些介绍 希望对大家有用-5 fpga development board schematic and on the introduction of fpga hope useful for all of us
pal_vedio
- 基于FPGA的pal制模拟视频显示程序，verilog Hdl-pal-d vedio display fpga verilog
DPLL
- 数字锁相环频率合成器的vhdl实现的源代码-Digital PLL Frequency Synthesizer vhdl source code to achieve