资源列表
VGA_rom_27704167
- vhdl (ps2接口） 实现rom 读取 -vhdl (ps2） for rom
ps2_mouse
- VHDL ps2接口 实现 鼠标传输 时序逻辑， 串口连接-vhdl for mouse(ps2)
ps2_keyboard
- vhdl for ps2 keyword vhdl for ps2 keyword -vhdl for ps2 keywordvhdl for ps2 keyword
gen_div
- 通用偶数分频器，通过输入频率较高的时钟信号，在设置分频参数后，得到较低频率的时钟信号。-gen div
UART
- UART Package Declaration with Receiver Transmitter !
Seven_Segment_LED
- numato labs code , in verilog or in vhdl , which is very useful for small projects
Main
- Sensor Project , Verilog
wulian_dingwenxin_3012204216
- 基于quartus2的环境，做的认真，实现了微波炉的开关温度设置等-Quartus2 based environment, do seriously, to achieve a switching temperature microwave ovens, etc.
mips_cpu_code_Rev_0.5
- vhdl MIPS CODE , WORKING GOOD
allcode
- Verilog Source Code Basys2 , SevenSegment and Switch LED Intraction
plj.FPGA
- 本频率计基于CPLD/FPGA实现。 50MHZ标准频率为CPLD内部时钟信号，被测方波为信号发生器产生的方波信号，显示电路由TTL芯片及七段数码管组成的电路，自校正输出由CPLD输出已知频率的测试方波信号，可将其输入至测试端口，进行系统精度校正。 -The frequency meter based on CPLD/FPGA implementation. 50MHZ standard CPLD internal clock signal frequency, square-wave test
jtd
- eda交通灯实验，在A方向和B方向各有红黄绿3盏灯，两个路口的红绿灯交叉循环，用Quartus--eda traffic light experiment in direction A and B directions are red yellow and three lights, two lights cross junction cycle, using Quartus-ii