资源列表
step_motor_fenpin
- 步进电机驱动，采用Verilog语言分频法设计，可实现一直转动。-Stepper motor drive, using Verilog language crossover method designed to achieve has been rotated.
shumaguan
- 七段数码管驱动，在DE2开发板上通过拨动开关输入数字，在数码管中显示-Seven-segment LED driver, the DE2 board to enter numbers by toggle switch in the digital tube display
cf_ad9129_ebz_edk_14_4_2013_03_12.tar
- FPGA+DDS+DAC,ADI参考设计-verification of AD9129-EVB based on FPGA
ppv2
- pipeline流水线用MIPS实现，用的是verilog。解决流水线的各种冲突。-pipeline pipeline with MIPS implementation, using verilog. Resolve conflicts pipeline.
fenpin
- 对m序列进行2ASK调制 包含分频器 m序列发生器 正弦信号发生器 二路选择器4个模块-process m sequence with 2Ask includes frequency divider, m sequence generator, sine signal generator and MUX
sell-machine
- verilog sell machine 通过robei和vivado设计的建议xilinx测试程序，有助于学习vivado和fpga-verilog vivado xilinx
Mojo-FSM
- Finit state machine proce-Finit state machine process
water_led
- Verilog语言编写，在FPGA 上实现流水灯。-Verilog language to achieve water lights on the FPGA.
Asynchronous
- 异步加法计数器，采用D触发器实现的二进制计数器-Asynchronous adding counter using D flip-flop to achieve binary counter
ren_gen
- xilinx vhdl code for random number generator and prime number check. it can be used for cryptography
Synchronous
- 同步加法计数器，采用D触发器实现的二进制计数器-Synchronous adding counters, D flip-flop implemented using binary counter
FSM
- 序列检测器，采用移位寄存器实现，检测特定序列“101011”-Sequence detector using a shift register implementation, detection of a specific sequence 101011