资源列表
FSM
- 序列检测器，采用有限状态机实现，检测特定序列“101011”- Sequence detector, finite state machine, detection of a specific sequence 101011
cymometer
- 频率计，用于对一个未知频率的周期信号进行频率测量，在1s 内对信号周期进行计数，得到周期信号的频率。- Frequency meter, for an unknown frequency of the periodic signal frequency measurement, in 1s signal cycle counts, to obtain the frequency of the periodic signal.
Blocking-Nonblocking
- blocking and non blocking statement in verilog example.
ALU
- Arithmetic and Logic Unit
sorter_block
- this is a code for a sorter block. read data a RAM and sort them. then write data in RAM-this is a code for a sorter block. read data a RAM and sort them. then write data in RAM
RS_232_Test
- this file is a driver for rs-232 protocol. tx and rx. working for as uart protocol
fifo
- FIFO FSM Implementation
pipeline_streamlined_divider
- pipeline_streamlined_divider, 一个流水线的除法器，使用Verilog HDL语言编写-pipeline_streamlined_divider， a divider using pipeline technology in verilog HDL language
pipeline_lut_multiplier
- pipeline_lut_multiplier, 一个使用查找表实现的流水线乘法器，本程序使用verilog HDL language 语言编写-pipeline_lut_multiplier ，a multiplier based on look up tablets ,and it is programing in verilog language
fifo_pipeline_booth_multiplier
- fifo_pipeline_modified_booth_multiplier一个使用FIFO的Booth乘法器，并且使用了流水线描述方式，本程序给予verilog 语言-fifo_pipeline_modified_booth_multiplier, a booth multiplier using pipeline technology in verilog HDL language
TimeQuest-diary
- 关于TimeQuest的时序分析日志，属于时序分析的基础部分，对学习时序分析有很大帮助-a learning diary about TimeQuest analyse
iic_100k
- 用verilog HDL语言描述的i2C总线程序-a iic_100k program using a verilog HDL