资源列表
fufenjieqi
- 基于FPGA的复分接器，包括了M序列码的产生，2路数据复接，数据分接（包括巴克码的判断）。-FPGA-based compound splitters, including M sequence code generation, 2 channel data multiplexing, data tap (including the Barker code to judge).
i2c_test
- IIC协议的verilog代码 值得学习！-IIC protocol verilog code worth learning!
Part5
- Display eight 7-segment displays on the DE2 board using Quartus -Display eight 7-segment displays on the DE2 board using Quartus II
mode1_master
- UART0 模式1主机程序TX0线为P0.0，RX0线为P0.1，TX0采用T2为波特率产生源，RX0采用T1为波特率产生源-UART0 mode, a host program TX0 line for the P0.0, the RX0 line for P0.1 obtained, TX0 as using T2 generation source for the baud rate, RX0 uses T1 for baud rate generator source
conter1
- 一个VHDL计数器。可进一步改装成实际的计数器使用-a VHDL counter. Can be further converted into actual use of the Counter
alu
- 硬件设计vhdl_cpu1,1. You may copy and distribute verbatim copies of this core, as long -- as this file, and the other associated files, remain intact and -- unmodified. Modifications are outlined below.-hardware design vhdl_cpu1, 1. You may copy and dist
divide
- It is n-bit sequential divider in verilog language
disp_on_ledspot
- LED点阵屏上文字显示实验 实验要求：在试验板的8×8的LED点阵屏上分别显示“PLD电子技术”。-LED dot matrix text display screen test test requirements: the test panels of 8 × 8 LED dot matrix display screen, respectively, " PLD electronic technology."
1
- ：频率计。具有4位显示，能自动根据7位十进制计数的结果，自动选择有效数据的 --高4位进行动态显示。小数点表示是千位，即KHz。
MPU707
- 固定乘法运算，用于FFT编程，是固定的乘法，对FFT运算比较有用-Fixed multiplication for FFT program, a fixed multiplication, more useful on the FFT operation
jpq
- 频率计。具有4位显示，能自动根据7位十进制计数的结果，自动选择有效数据的高4位进行动态显示。小数点表示是千位，即KHz。-Frequency counter. 4 shows automatically based on the count of seven decimal automatically select 4 of the valid data for dynamic display. Decimal point, said one thousand, that is, KHz,.
divid
- 基于VHDL的divided建模，方便调用，主要是除法运算，用于数据移位-Divided modeling based on VHDL, call the main division operation is used to shift data