资源列表
AsynCFIFO
- 跨时钟域，异步的FIFO，利用指针移动，数据不移动，通过两级锁存消除跨时钟域的信号竞争-Cross clock domains and asynchronous FIFO, use the pointer to move, do not move the data, eliminating cross clock domain signal through a two-stage competition latch
DC-Adder_Array
- 要求采用快速进位链（Look Ahead）设计一个21位加法器； 2) 采用结构化的设计方法，所有加法器均采用步骤1）的21位加法器； 3) 在加法器阵列中加入流水线结构（Pipelinc），输入连续送数，输出连续出结果，流水线填满后每拍输出一个结果； -1) requires the use of fast carry chain (Look Ahead) design a 21-bit adder 2) the use of structured design metho
0714
- 这是一个简单的基于VHDL的初学者编写的功能丰富的电子钟.-This is a simple VHDL based program for beginners to write a rich electronic clock.
eetop.cn_dds
- 基于verilog的DDS设计,内附代码,仿真环境等说明-the DDS design based on verilog
DATA_SEND1
- vhdl code for w300 and I doenload @ chines site
dual_priority_encoder2
- 这是一个组合电路，实现的是8位的优先编码器。-this is a combination circuit,Implement the eight priority encoder，
free_running_counter
- 这是一个计数器，可以实现自加1操作的自动计数器。-this is a counter ,By Mika realization operational counter add 1.
FIFO_BUFFER
- 先入先出的缓冲器，可以实现8位的读、写数据操作。-buffer of first-in first-out circuit can ，Realization 8-bit. The number of read and wirte operation is stopped.
stopwatch_if
- 用IF语句实现秒表功能的代码，显示范围在000至9-Stopwatch function code with the IF statement, displayed in the range of 000 to 99.9.
verilog
- verilog的基础入门资料，很适合初学者学习参考-verilog basis for introductory information, it is suitable for beginners to learn reference
vga_verilog
- 在DE1-SOC上运行的verilog HDL代码，可以驱动VGA显示彩条。quartus II 14.0可以直接使用-Verilog HDL code running on DE1-SOC, can drive VGA display color bars. quartus II 14.0 can be used directly
SD_Card
- sdhc卡spi扇区读verilog例程。包含sdhc卡初始化模块及一个扇区读模块，扇区读完数据放在一个fifo中缓存，为之后的工作做准备，可以集成到自己的项目中。已经在闪迪8Gsdhc卡上亲测成功-sdhc card sector read spi verilog routine. Initialization module and a read module contains sdhc card sector, the sector read data in a cache fifo in