资源列表
7210040034_Yasifa-Rakhma_ProjectAkhir
- REPORT OF Embedded System VHDL 3-to-8 Decoder using a For-Loop
test-led
- 流水灯程序，利用了VHDL，虽然程序比较简短，但是，用的还是比较经典的-Light water program, the use of VHDL, although the procedure is relatively short, but with quite classic
YCbCr2RGB
- YCbCr turn RGB module, to apply to the project.
VHDL_Multiplier
- 三种 VHDL 实现乘法器的方法，可以用于学习FPGA的时序、组合电路，同时附带了 TestBench 程序-Three kinds of methods to achieve multiplier in VHDL, with TestBench
Turbo_ECC
- However, since they use general priors for all kinds of noisy images, without considering the content of the noisy image, they soon reach their performance limitation (comparable to BM3D) and tend to introduce artifacts if the noisy image doe
Cordic
- block-matching 3D filtering (BM3D) [2], and low-rank regularization [3], single-image based denoising performance has greatly improved, with image details well recovered when the image is slightly noisy. However, with the increase of noise le
jingsai
- 微机原理课程实验应用，竞赛抢答器的设计，文本档-Microcomputer Principle Course Laboratory applications, Contest Responder design, text files
AES
- AES的加密解密verilog全部源代码-AES encryption and decryption verilog full source code
shuzishizhong
- 基于DE2-115开发板设计的一个数字钟，能进行正常的小时、分、秒计时功能，并分别由开发板上面的数码管显示秒（60s）、分（60min）、小时（24hours）的时间。并具有手动调整时间的功能-DE2-115 board design based on a digital clock, and enables the normal hours, minutes, seconds chronograph function, and were above the development board
FPGA--Hammingcode
- FPGA实现扩展的海明校验码，本程序用于冗余存储器的校验-Hamming Code
emif
- 异步EMIF接口，16bit，FPGA程序。-asynchronous emif，16bit，FPGA program
FIRfilterverilogHDL
- FIR滤波器的verilog HDL代码示例，以16阶为例-Verilog HDL code for fir filter