资源列表
PLL_myprj
- FPGA做锁相环，里面用到很多IP核，详细注释，希望大家喜欢-Do FPGA phase-locked loop, which uses a lot of IP cores, detailed notes, I hope you like
new_2ask
- 做课程设计时写的，关于2ASK的调制和解调，里面代码测试过，完好-Do curriculum design written about 2ASK modulation and demodulation, which tested the code, intact
NCO_DDS
- 自己写的代码，用了NCO核组合的DDS，测试过，希望对大家有所帮助-Write your own code, using a combination of NCO nuclear DDS, tested, we hope to help
fpga_sin_fangbo_vga_sanjiaobo
- FPGA作为DDS，三角波，方波，正弦波，然后可以再VGA上显示 里面注释详细，已经仿真，验证，测试了-FPGA as DDS, triangle wave, square wave, sine wave, then you can then VGA detailed notes on the inside, has simulation, verification, testing shows
FPGA_daohang
- 一些FPGA代码，里面有很多值得大家参考的代码，本人整理了一周，弄的-Some FPGA code, there are a lot of code is worth your consideration, I am finishing a week, get
QPSK
- 四相相移键控，QPSK调制与解调器的设计，通过仿真解调出正确的信息码-Quadrature phase shift keying, QPSK modulation and demodulation of the design, the simulation code to demodulate the correct information
vdemo_p107_traligt_2015-07-06
- 自己写的教科书中的例子，《verilog hdl数字设计与综合（第二版）》107页，交通灯的例子。主干路与乡村路交通灯控制。verilog源码，modelsim仿真通过。--verilog, modelsim, traffic light control
EXAMPLES-ON-SYSTEM-VERILOG.tar
- THIS FILE CONTAINS AROUND 20 USEFUL EXAMPLES ON SYSTEM VERILOG (MEMORY-ARRAYS,LOGICS,DATATYPES ETC.)-THIS FILE CONTAINS AROUND 20 USEFUL EXAMPLES ON SYSTEM VERILOG (MEMORY-ARRAYS,LOGICS,DATATYPES ETC.)
CFO
- zedboard/AD9361平台进行无线收发，在接收端进行频偏估计和补偿的Verilog参考代码。-zedboard/AD9361 platform for wireless transceiver, the receiver frequency offset estimation and compensation, you can refer to the Verilog code.
ov7670-1
- ov7670摄像头FPGA数据采集、显示模块，测试可用-ov7670 camera, verilog code, video capture and display
deinterleaver_new
- fpga implementation of wimax deinterleaver address generator using vhdl cod
booth_recoding
- fpga implementation of booth recoding algorithm using verilog code