资源列表
x7seg
- 一个实用的FPGA数码管显示驱动，移植性比较好，Verilog语言编写，实测通过，可直接作为子模块调用-A practical FPGA digital display driver, portability is better, Verilog language, measured by, as a sub-module can directly call
ddr3_demo_verilog
- 基于Verilog HDL的ddr3控制器，适用于lattice的ECP3系列-ddr3 controller based on Verilog HDL，used in lattice ECP3 serial FPGA
DDR2-verilog
- ddr2的Verilog代码，包括时序控制，数据读取，利用verilog编写的ddr2控制器，在spartan6板子上得以验证，成功实现了FPGA与DDR2的通信。-ddr2 of Verilog code, including timing control, data is read using verilog prepared ddr2 controller board on spartan6 be verified, the successful implementation of the
FIFO_Memory
- FPGA memory implementation
VHDL_Examples_DE1_SoC
- DE1-COS学习例程,用VHDL语言为FPGA写入按键显示程序，有助于学习-DE1- COS learning routines, for FPGA with VHDL language display program written to buttons, helps to learn
FIFO
- FIFO先进先出，控制时序，对urat、SDRAM、DAC等时序理解都有帮助-FIFO FIFO control the timing of urat, SDRAM, DAC and other timing understanding have helped
lcd_system
- lcd系统：包含了图片显示、汉字字库、PS2输出的lcd显示系统。-lcd system: Contains pictures show, Chinese character, lcd PS2 output display system.
calculator
- 能够实现8位的无符号数的乘除法，模拟了笔算的过程-Unsigned 8-bit multiplication and division can be achieved, simulation the written calculation process
wdog_sp805
- 看门狗模块是一个AMBA从属模块连接到高级 外设总线（APB）。看门狗模块包括一个32位的递减计数器用 可编程超时间隔具有产生中断和能力 对超时复位信号。它的目的是要使用到复位应用于在一个系统 事件的软件故障。-The Watchdog module is an AMBA slave module and connects to the Advanced Peripheral Bus (APB). The Watchdog module consists of a 32-b
log_generator
- log10 generator in vhdl. simulated in Modelsim
tb_contrast_stretch
- contrast strech for image pixles
tlv5638_ise12migration
- 使用SPI通信协议，quartusII开发环境，编写5638驱动-Using SPI communication protocol, quartusII development environment, the preparation of 5638 drivers